When compared with conventional floating-gate memories, floating-gate memories that are based on nanocrystals have the following advantages: (1) They are less susceptible to defects in the program oxide since the charge is stored on isolated nanocrystal sites. (2) They can store two bits per cell by reversing the role of the source and drain since the charge is localized at the injection point. (3) They have potentially lower voltage operation and higher retention.
In previous reports, see, for example, S. Tiwari, et al., Appl. Phys. Lett., 68, p. 1377 (1996) and M. L. Ostraat, et al., Appl. Phys. Lett., 79, 433 (2003), the nanocrystals were typically formed by spontaneous decomposition during chemical vapor deposition (CVD) or aerosol deposition. This led to a wide spread in the nanoparticles size and position. More recently, Guarini, et al. IEDM 2003 p. 541 (2003) have demonstrated a nanocrystal-based floating-gate memory where the nanocrystals were defined by a self-assembled polymer mask and conventional reactive ion etching (RIE).
The technique described by Guarini, et al. improved the nanocrystals uniformity, but has the following drawbacks: First, the nanocrystals are cut out of a continuous film of amorphous silicon or polycrystalline silicon and hence the nanocrystals may be comprised of several single-crystal grains that are lumped together. Therefore, charge storage in each of the lumped nanocrystals is likely to depend on grain boundaries and the surface of the nanocrystals, which properties are difficult to control. Second, the size of the nanocrystals is defined by the pores size in the polymer mask, which is dependent on the spacing between pores. Thus, independent control over the size of the nanocrystals and the spacing between nanocrystals is not possible. Third, the nanocrystals cannot be formed directly with the polymer mask since the mask defines the negative image of the nanocrystals (i.e., pores). As a result, a two step reactive-ion etch (RIE) process is required. Additionally, RIE damage may be another factor for charge trapping on the nanocrystal surface. Fourth, passivation of the nanocrystal surface is very limited since the nanocrystals are formed by filling cavities in an oxide hard mask.
In view of the drawbacks mentioned above, there is still a need for providing nanocrystal-based floating-gate non-volatile memories in which the nanocrystals are fabricated by techniques which avoid the problems of prior art fabrication techniques.